INTRODUCTION TO COMPUTERS
COMPUTER ARCHITECTURE AND ORGANIZATION
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Question
[CLICK ON ANY CHOICE TO KNOW THE RIGHT ANSWER]
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A four stage pipeline has the stage delays as 150, 120, 160 and 140 ns respectively. Registers are used between the stages and have a delay of 5 ns each. Assuming constant clocking rate, the total time taken to process 1000 data items on the pipeline will be-
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130.4 microseconds
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165.5 microseconds
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145 microseconds
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158.4 microseconds
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Explanation:
Detailed explanation-1: -Q5. The stage delays in a 4-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. The throughput increase of the pipeline is percent.
Detailed explanation-2: -The time delay for the four segments are : t1= 50ns, t2 = 30ns, t3 = 95ns, t4 = 45ns. The interface register delay tr = 5ns.
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