COMPUTER FUNDAMENTALS

Previous
Next

INTRODUCTION TO COMPUTERS

COMPUTER ARCHITECTURE AND ORGANIZATION

Question [CLICK ON ANY CHOICE TO KNOW THE RIGHT ANSWER]
Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of 4. The same processor is upgraded to a pipelined processor with five stages but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume there are no stalls in the pipeline. The speed up achieved in this pipelined processor is-
A
3.0
B
2.2
C
3.2
D
2.0
Explanation: 

Detailed explanation-1: -latency is for Instruction decode. Hence, clock cycle time for pipelined processor is: 350ps. For a non-pipelined processor cycle time can be determined by adding the sum for all stages.

Detailed explanation-2: -A non-pipelined processor has a clock rate of 2.5 GHz and an average CPI (cycles per instruction) of 4. An upgrade to the processor introduces a five-stage pipeline. However, due to internal pipeline delays, such as latch delay, the clock rate of the new processor has to be reduced to 2 GHz.

Detailed explanation-3: -Non-pipeline time=50nsecpipeline CPI = 0.8 * 1 + 0.2 * (1 + 3)=1.6pipeline time = 1.6*10 nsec= 16 nsecSpeed up=non-pipeline timepipeline time=5016=3.125. Q. Consider a pipeline which takes 7 cycles to executes 1st instruction. the same task can be completed in a non-pipelined system with x cycles.

There is 1 question to complete.
Previous
Next