INTRODUCTION TO COMPUTERS
COMPUTER ARCHITECTURE AND ORGANIZATION
|
Question
[CLICK ON ANY CHOICE TO KNOW THE RIGHT ANSWER]
|
|
|
31.33%
|
|
|
32.33%
|
|
|
33.33%
|
|
|
34.33%
|
Detailed explanation-1: -Correct answer is ‘= 33.33%’. Can you explain this answer? The stage delays in a-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionality equivalent design involving two stages with respective delays 600 and 350 picoseconds.
Detailed explanation-2: -All the stages in a non-uniform delay pipeline will complete their operations by taking different times. The cycle time in this pipeline is described as follows: Cycle Time (Tp) = Maximum (Stage Delay) For example: Suppose we have four stages, which contain stage delay as 1 ns, 2 ns, 3 ns, and 4 ns.
Detailed explanation-3: -Each stage of the pipeline is only as fast as the slowest stage. The calculation for the latency expresses this by taking the maximum delay ( max(D1, D2, D3, D4) ) and multiplying it by N, which is the number of stages. Thus: N*max(D1, D2, D3, D4) .