INTRODUCTION TO COMPUTERS
COMPUTER ARCHITECTURE AND ORGANIZATION
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Question
[CLICK ON ANY CHOICE TO KNOW THE RIGHT ANSWER]
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What will be the output from a D flip-flop if D = 1 and the clock is low?
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1
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No change
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0
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3
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Explanation:
Detailed explanation-1: -Earlier, the DFF is in a clear state (output is 0). So, if D = 1 then in the next stage output will be 1 and hence the stage will be changed.
Detailed explanation-2: -D flip flop has only one input terminal. The output of the D flip flop will be the same as the input. Hence, it is used in delay circuits. The circuit is as shown below.
Detailed explanation-3: -The output of a D-latch is high when both the input (CLK 1) and clock (CLK 2) are high i.e. the output wave-form is AND condition of the 2 Clock input.
There is 1 question to complete.