COMPUTER SCIENCE AND ENGINEERING
COMPUTER ARCHITECTURE
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Question
[CLICK ON ANY CHOICE TO KNOW THE RIGHT ANSWER]
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10, 17
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10, 22
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15, 17
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5, 15
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Detailed explanation-1: -Number of blocks = cache size/block size = 32KB/32 = 1024 bytes. So, indexing requires 10 bits. Number of OFFSET bits required to access 32 bit block = 5. So, number of TAG bits = 32-10-5 = 17.
Detailed explanation-2: -Consider a direct mapped cache of size 32KB with block size 32 bytes. The CPU generates 32 bit addresses. The number of bits needed for cache indexing and the number of tag bits are respectively. No worries!
Detailed explanation-3: -BTW the answer according to the textbook is 147 Kibibits (18.4 KiB).
Detailed explanation-4: -In a 128 KB direct-mapped cache with 8 word (32 byte) cache lines, there are 4×2 10 = 2 12 cache lines (128KB/32B).
Detailed explanation-5: -A direct-mapped cache is the simplest approach: each main memory address maps to exactly one cache block. For example, on the right is a 16-byte main memory and a 4-byte cache (four 1-byte blocks). Memory locations 0, 4, 8 and 12 all map to cache block 0. Addresses 1, 5, 9 and 13 map to cache block 1, etc.