MCQ IN COMPUTER SCIENCE & ENGINEERING

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COMPUTER SCIENCE AND ENGINEERING

COMPUTER ARCHITECTURE

Question [CLICK ON ANY CHOICE TO KNOW THE RIGHT ANSWER]
Consider a machine with a byte addressable main memory of 2 ^ 20 bytes, block size of 16 bytes and a direct mapped cache having 2 ^ 12 cache lines. Let the addresses of two consecutive bytes in main memory be (E201F)16 and (E2020)16. What are the tag and cache line address (in hexadecimal) for main memory address (E201F)16? ( GATE 2015 )
A
E, 201
B
F, 201
C
E, E20
D
2, 01F
Explanation: 

Detailed explanation-1: -Ans: We know that 64 KB is 64K words, which is 2 to the power 14 words, and, with a block size of one word, 2 to the power 14 blocks. Each block hs 32 bits of data plus a tag, which is 32-14-2 bits, plus a valid bit. Thus, the total cache size is (2 to the power 14)*49= 784 bits or 98KB for a 64-KB cache.

Detailed explanation-2: -You have 16 kB = 16*1024 = 16384 bytes of data . Since word has 4 bytes, this makes 16384 bytes / 4 bytes per word = 4096 words . Block size is 4 words, that makes 4096 words/4 words per block = 1024 (2^10) blocks . This means 10 bits are used for the index.

Detailed explanation-3: -Here is a 256-entry cache that has 64-byte block entries. That is, each block is 16 words wide.

Detailed explanation-4: -In a virtual memory system, size of virtual address is 32-bit, size of physical address is 30-bit, page size is 4 Kbyte and size of each table entry is 32-bit. The main memory is byte addressable.

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