COMPUTER SCIENCE AND ENGINEERING
COMPUTER ARCHITECTURE
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Detailed explanation-1: -ARM processors have 37 registers. The registers are arranged in partially overlapping banks. There is a different register bank for each processor mode. The banked registers give rapid context switching for dealing with processor exceptions and privileged operations.
Detailed explanation-2: -ARM v6/v7 maintains a status register called the CPSR (current program status register) that holds four status bits, negative (N), zero (Z), carry (C), and overflow (O). These bits can be used for conditional execution of subsequent instructions.
Detailed explanation-3: -The PSRs are subdivided into three status registers: Application Program Status register (APSR) Interrupt Program Status register (IPSR) Execution Program Status register (EPSR)
Detailed explanation-4: -General-purpose registers With the exception of ARMv6-M and ARMv7-M based processors, there are 30 (or 32 if Security Extensions are implemented) general-purpose 32-bit registers, that include the banked SP and LR registers.
Detailed explanation-5: -The ARM7TDMI processor has seven modes of operation: User mode is the usual ARM program execution state, and is used for executing most application programs. Fast Interrupt (FIQ) mode supports a data transfer or channel process.