MCQ IN COMPUTER SCIENCE & ENGINEERING

Detailed explanation-1: -The RISC Approach Because there are more lines of code, more RAM is needed to store the assembly level instructions. The compiler must also perform more work to convert a high-level language statement into code of this form.

Detailed explanation-2: -The RISC architecture will need more working (RAM) memory than CISC to hold values as it loads each instruction, acts upon it, then loads the next one. The CISC architecture can execute one, albeit more complex instruction, that does the same operations, all at once, directly upon memory.

Detailed explanation-3: -RISC provides high performance per watt for battery operated devices where energy efficiency is key. A RISC processor executes one action per instruction. By taking just one cycle to complete, operation execution time is optimized. Because the architecture uses a fixed length of instruction, it’s easier to pipeline.

Detailed explanation-4: -Following are the main characteristics of the RISC processor: The length of the code is shorts, so it requires very little RAM. CISC or complex instructions may take longer than a single clock cycle to execute the code. Less instruction is needed to write an application.