COMPUTER SCIENCE AND ENGINEERING
COMPUTER ORGANIZATION
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Question
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Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of 4. The same processor is upgraded to a pipelined processor with five stages but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume there are no stalls in the pipeline. The speed up achieved in this pipelined processor is-
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3.0
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2.2
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3.2
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2.0
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Explanation:
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