MCQ IN COMPUTER SCIENCE & ENGINEERING

Detailed explanation-1: -It is in the sense that if the output Q = 0 then the second output Q’ = 1 and vice versa. Explanation: In S-R flip-flop, if Q = 0 the output is said to be reset and set for Q = 1. Explanation: The output of latches will remain in set/reset untill the trigger pulse is given to change the state.

Detailed explanation-2: -The SR flip flop is a 1-bit memory bistable device having two inputs, i.e., SET and RESET. The SET input ‘S’ set the device or produce the output 1, and the RESET input ‘R’ reset the device or produce the output 0.

Detailed explanation-3: -Flip-flops are the Sequential circuit. Flip-flops can store a 1-bit of information. For flip-flop, its input can affect the output only when the enable signal changes (falling edge or rising edge). When a flip-flop is reset its output will be Q = 0, Q̅ = 1.

Detailed explanation-4: -The RS flip-flop is said to be in an invalid condition if both the set and reset inputs are deactivated simultaneously, i.e. when both S = R = 0.

Detailed explanation-5: -When the input state R = 0 and S = 0 is an invalid condition and must be avoided because this will give both outputs Q and Ǭ at logic level “1” at the same time and the necessary condition is that Q to be the inverse of Ǭ. The flip-flop goes to an unstable state as both the output goes LOW.