COMPUTER SCIENCE AND ENGINEERING
COMPUTER ORGANIZATION
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Question
[CLICK ON ANY CHOICE TO KNOW THE RIGHT ANSWER]
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31.33%
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32.33%
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33.33%
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34.33%
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Detailed explanation-1: -The first stage (with delay 800 picoseconds) is replaced with a functionality equivalent design involving two stages with respective delays 600 and 350 picoseconds. The throughput increase of the pipeline is percent. Correct answer is ‘= 33.33%’.
Detailed explanation-2: -The stage delays in a 4-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds.
Detailed explanation-3: -A 4-stage pipeline has the stage delays as 150, 120, 160 and 140 nanoseconds respectively. Registers that are used between the stages have a delay of 5 nanoseconds each. Assuming constant clocking rate, the total time taken to process 1000 data items on this pipeline will be. No worries!
Detailed explanation-4: -What is the best speedup you can get by pipelining it into 5 stages? 5x speedup. The new latency would be 10ns/5 = 2ns.
Detailed explanation-5: -Thus first process will take 4 clock cycles and remaining processes will be completed one process each clock cycle. Thus for above example total time required to complete whole job will be 9 clock cycles ( with pipeline organization) instead of 24 clock cycles required for non pipeline configuration.