COMPUTER SCIENCE AND ENGINEERING
DIGITAL LOGIC
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Question
[CLICK ON ANY CHOICE TO KNOW THE RIGHT ANSWER]
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J = 1, K = 1
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J = 1, K = 0
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J = 0, K = 1
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J = 0, K = 0
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Detailed explanation-1: -Explanation: If J = 0, K = 0, the output remains unchanged. This is the memory storing state. Explanation: The flip flop is sensitive only to the positive or negative edge of the clock pulse. So, the flip-flop toggles whenever the clock is falling/rising at edge.
Detailed explanation-2: -If J and K are both low then no change occurs. If J and K are both high at the clock edge then the output will toggle from one state to the other. It can perform the functions of the set/reset flip-flop and has the advantage that there are no ambiguous states.
Detailed explanation-3: -Explanation: If J=0 & K=0, the output will be as: Q(n)=0, Q(n+1)=0 and it is fed into both the AND gates which results as S=0 & R=X(i.e. don’t care).
Detailed explanation-4: -When J and K are tied together or set at 1 then the present state is equal to the previous state and gets complimented that 0 becomes 1 or 1 becomes 0. Therefore, a J-K flip flop made to toggle ? is J=1, K=1. Hence, option (D) is the correct answer.
Detailed explanation-5: -This implies that if J = 0 and K = 1, then the flip-flop resets (Q = 0 and Q̅ = 1). Next if J = 1, K = 0, Q = 1 and Q̅ = 0, then X1 = X2 = 0 which results in Q = 1 (and thus Q̅ = 0).