COMPUTER SCIENCE AND ENGINEERING
DIGITAL LOGIC
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Question
[CLICK ON ANY CHOICE TO KNOW THE RIGHT ANSWER]
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J = 0, K = 0
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J = 1, K = 1
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J = 1, K = 1
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J = 1, K = 0
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Detailed explanation-1: -When J and K are tied together or set at 1 then the present state is equal to the previous state and gets complimented that 0 becomes 1 or 1 becomes 0. Therefore, a J-K flip flop made to toggle ? is J=1, K=1. Hence, option (D) is the correct answer.
Detailed explanation-2: -How is a J-K flip-flop made to toggle? Explanation: When j=k=1 then the race condition is occurs that means both output wants to be HIGH. Hence, there is toggle condition is occurs, where 0 becomes 1 and 1 becomes 0.
Detailed explanation-3: -J represents SET, and ‘K’ represents CLEAR. In the JK flip-flop, the ‘S’ input is known as the ‘J’ input, and the ‘R’ input is known as the ‘K’ input. The output of the JK flip-flop does not modify if both ‘J’ and ‘K’ are ‘0’. If both the inputs are ‘1’, then the output dial to its free.
Detailed explanation-4: -However, if both the J and K inputs are HIGH at logic “1” (J = K = 1), when the clock input goes HIGH, the circuit will “toggle” as its outputs switch and change state complementing each other. This results in the JK flip-flop acting more like a T-type toggle flip-flop when both terminals are “HIGH”.
Detailed explanation-5: -The master flip flop toggles on the clock’s positive transition when the inputs J and K set to 1. At that time, the slave flip flop toggles on the clock’s negative transition. The flip flop will be disabled, and Q remains unchanged when both the inputs of the JK flip flop set to 0.