COMPUTER SCIENCE AND ENGINEERING
DIGITAL LOGIC
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Question
[CLICK ON ANY CHOICE TO KNOW THE RIGHT ANSWER]
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when the gate is LOW
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when the gate is HIGH
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both of the above
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neither of the above
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Detailed explanation-1: -Master flip-flop is triggered by the external clock pulse train while the slave is activated at its inversion that is if the master is positive edge-triggered, then the slave is negative-edge triggered.
Detailed explanation-2: -Then, the circuit accepts input data when the clock signal is “HIGH”, and passes the data to the output on the falling-edge of the clock signal. In other words, the Master-Slave JK Flip flop is a “Synchronous” device as it only passes data with the timing of the clock signal.
Detailed explanation-3: -The master flip flop toggles on the clock’s positive transition when the inputs J and K set to 1. At that time, the slave flip flop toggles on the clock’s negative transition. The flip flop will be disabled, and Q remains unchanged when both the inputs of the JK flip flop set to 0.
Detailed explanation-4: -Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input data is read during the entire time the clock pulse is at a LOW level.
Detailed explanation-5: -Hence a master slave flip-flop completes its operation only after the appearance of one full clock pulse for which they are known as pulse – triggered flip flops. So, the right answer is option no. B .