COMPUTER SCIENCE AND ENGINEERING
DIGITAL LOGIC
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Question
[CLICK ON ANY CHOICE TO KNOW THE RIGHT ANSWER]
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Setup time
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Hold time
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Clock time
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None of the above
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Detailed explanation-1: -Hold time, tH is the time following the active transition of the CLK during which the control input must kept at the proper level.
Detailed explanation-2: -Hold time is the minimum amount of time required for the input to a Flip-Flop to be stable after a clock edge. In the figure, the green area represents the tsu or Setup Time. The blue area represents the th or Hold Time. In these areas, the data into the Flip-Flop must be a stable 0 or a 1 or bad things will happen…
Detailed explanation-3: -In other words, each flip-flop (or any sequential element, in general) needs some time for the data to remain stable before the clock edge arrives, such that it can reliably capture the data. This duration is known as setup time.
Detailed explanation-4: -Setup and hold checks are the most common types of timing checks used in timing verification. Synchronous inputs (e.g. D) have Setup, Hold time specification with respect to the clock input. These checks specify that the data input must remain stable for a specified interval before and. after the clock input changes.
Detailed explanation-5: -Explanation: A clock must be used along with synchronous control inputs to trigger a change in the flip flop. These flip – flops may be edge – triggered or level – triggered. A change should occur only when the clock changes from 0 to 1 or vice versa.