MCQ IN COMPUTER SCIENCE & ENGINEERING

Detailed explanation-1: -only thing you can do to avoid this is to make sure that, both inputs doesn’t go high at same time. To overcome this we go for Edge triggered flip flop(D flip flop is one of its types). An Edge Triggered flip flop changes its state either at raising edge or falling edge of the clock pulse of control input.

Detailed explanation-2: -The limitation with a S-R flip-flop using NOR and NAND gate is the invalid state. This problem can be overcome by using a stable SR flip-flop that can change outputs when certain invalid states are met, regardless of the condition of either the Set or the Reset inputs.

Detailed explanation-3: -Detailed Solution When the S and R inputs of an SR flipflop are at logical 1, then the output becomes unstable and it is known as a race condition. So, the main disadvantage of the SR flip flop is invalid output when both inputs are high.

Detailed explanation-4: -If the clock on or high time is less than the propagation delay of the flip flop then racing can be avoided. This is done by using edge triggering rather than level triggering. If the flip flop is made to toggle over one clock period then racing can be avoided.

Detailed explanation-5: -A J-K flip-flop is nothing more than an S-R flip-flop with an added layer of feedback. This feedback selectively enables one of the two set/reset inputs so that they cannot both carry an active signal to the multivibrator circuit, thus eliminating the invalid condition.