COMPUTER SCIENCE AND ENGINEERING
DIGITAL LOGIC
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Question
[CLICK ON ANY CHOICE TO KNOW THE RIGHT ANSWER]
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Clock signal
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Set state
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Reset state
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None of the above
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Detailed explanation-1: -The normal data inputs to a flip flop (D, S and R, or J and K) are referred to as synchronous inputs because they have an effect on the outputs (Q and not-Q) only in step, or in sync, with the clock signal transitions.
Detailed explanation-2: -The circuit is controlled by the synchronising clock signal and the memory is realised with edge-triggered flip-flops, changes taking place on either the leading or trailing edge of a clock pulse.
Detailed explanation-3: -The flip-flop can be triggered by a raising edge (0->1, or positive edge trigger) or falling edge (1->0, or negative edge trigger).
Detailed explanation-4: -Asynchronous inputs are those inputs that can affect the output state of the flip-flop independent of a clock or timing pulse. Synchronous inputs do not have direct control of the output. They can only affect the output in conjunction with a clock pulse.