COMPUTER SCIENCE AND ENGINEERING
DIGITAL LOGIC
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Question
[CLICK ON ANY CHOICE TO KNOW THE RIGHT ANSWER]
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S=0, R=0
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S=0, R=1
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S=1, R=0
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S=1, R=1
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Detailed explanation-1: -Hence, in SR latch S = 1 and R = 1 is not a valid state.
Detailed explanation-2: -Explanation: In a NAND based S-R latch, If S’=0 & R’=0 then both the outputs (i.e. Q & Q’) goes HIGH and this condition is called an ambiguous/forbidden state. This state is also known as an Invalid state as the system goes into an unexpected situation.
Detailed explanation-3: -S=1, R=1 is state forbidden in SR flip flop. The flip flop does not get damaged in forbidden state (S=R=1). It is called forbidden because there is no definitive gurantee of a fixed output.
Detailed explanation-4: -For this reason, having both S and R equal to 1 is called an invalid or illegal state for the S-R multivibrator. Otherwise, making S=1 and R=0 “sets” the multivibrator so that Q=1 and not-Q=0. Conversely, making R=1 and S=0 “resets” the multivibrator in the opposite state.
Detailed explanation-5: -When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR logic gates. The stored bit is present on the output marked Q.