MICROPROCESSOR AND MICROCONTROLLER

Detailed explanation-1: -Pipeline: The processing of instructions is broken down into smaller units that can be executed in parallel by pipelines. The pipeline advances by one step on each cycle for maximum throughput.

Detailed explanation-2: -The three instructions are placed into the pipeline sequentially. In the first cycle the core fetches the ADD instruction from memory. In the second cycle the core fetches the SUB instruction and decodes the ADD instruction. In the third cycle, both the SUB and ADD instructions are moved along the pipeline.

Detailed explanation-3: -A coprocessor extends the processing features of a core by extending the instruction set or by providing configuration registers.

Detailed explanation-4: -The ARMv7 architecture uses general-purpose register R14 as the link register, OpenRISC uses register r9, and SPARC uses “output register 7” or o7. Some architectures have two link registers: a standard “branch link register” for most subroutine calls, and a special “interrupt link register” for interrupts.

Detailed explanation-5: -LDRB (8-bit, zero extended). LDRSB (8-bit, sign extended). LDRH (16-bit, zero extended). LDRSH (16-bit, sign extended).