MICROPROCESSOR AND MICROCONTROLLER

DMA CONTROLLER

ARCHITECTURE OF 8085

Question [CLICK ON ANY CHOICE TO KNOW THE RIGHT ANSWER]
These are the active-low DMA acknowledge lines, which updates the requesting peripheral about the status of their request by the CPU.
A
DRQ0-DRQ3
B
DACKo-DACK3
C
Do-D7
D
Ao-A3
Explanation: 

Detailed explanation-1: -DACKo − DACK These are the active-low DMA acknowledge lines, which updates the requesting peripheral about the status of their request by the CPU.

Detailed explanation-2: -Bus Request-We use bus requests in the DMA controller to ask the CPU to relinquish the control buses. Bus Grant-CPU activates bus grant to inform the DMA controller that DMA can take control of the control buses. Once the control is taken, it can transfer data in many ways.

Detailed explanation-3: -DMA sends read control signal to peripheral device and puts the destination address and read signal on address and control buses for memory. Data transfers from peripheral to memory directly. As each byte transferred, the destination address is incremented by 1.

Detailed explanation-4: -Answer is D). The HOLD signal as an input to the processor is used to request a DMA action. The HLDA signal as an output that acknowledges the DMA action.

There is 1 question to complete.