ARM PROCESSOR
ARCHITECTURE OF 8085
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Question
[CLICK ON ANY CHOICE TO KNOW THE RIGHT ANSWER]
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CPSR has ____ interrupt mask bits.
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2
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5
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6
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4
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Explanation:
Detailed explanation-1: -The execution state bits are the IT[7:0], J, E, and T bits. In exception modes you can read or write these bits in the current SPSR. In the CPSR, unless the processor is in Debug state: The execution state bits, other than the E bit, are RAZ when read by an MRS instruction.
Detailed explanation-2: -The Current Program Status Register (CPSR) holds processor status and control information.
Detailed explanation-3: -CPSR fields are divided in to four fields, each 8-bit wide: flags, status, extension, and control.
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