MICROPROCESSOR AND MICROCONTROLLER

Detailed explanation-1: -The SPSR is used to store the current value of the CPSR when an exception is taken so that it can be restored after handling the exception. Each exception handling mode can access its own SPSR. User mode and System mode do not have an SPSR because they are not exception handling modes.

Detailed explanation-2: -This is an application-level alias for the Current Program Status Register (CPSR). The system level view of the CPSR extends the register, adding system level information. Every mode that an exception can be taken to has its own saved copy of the CPSR, the Saved Program Status Register (SPSR), as shown in Figure 10.2.

Detailed explanation-3: -The CPSR contains condition code flags, interrupt disable bits, current processor mode and other control and status information. Each exception mode contains a saved program status register (SPSR). It is responsible for holding the value of CPSR in case the exception occurs.

Detailed explanation-4: -The CPSR (current programme status register) on ARMv6/ARMv7 keeps track of four status bits: negative (N), zero (Z), carry (C), and overflow (O) (O). These bits can be utilized to execute following instructions conditionally. The bits are set according to the most recent ALU instruction with the unique “s” suffix.

Detailed explanation-5: -The Linux/ARM embedded platform ARM v6/v7 maintains a status register called the CPSR (current program status register) that holds four status bits, negative (N), zero (Z), carry (C), and overflow (O). These bits can be used for conditional execution of subsequent instructions.