DMA CONTROLLER
ARCHITECTURE OF 8085
Question
[CLICK ON ANY CHOICE TO KNOW THE RIGHT ANSWER]
|
|
HLDA
|
|
HOLD
|
|
RQ/GT
|
|
READY
|
Detailed explanation-1: -The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to assert the HLDA. Then the microprocessor tri-states all the data bus, address bus, and control bus. The CPU leaves the control over bus and acknowledges the HOLD request through HLDA signal.
Detailed explanation-2: -Burst mode DMA: CPU can be put on hold while the DMA transfer occurs and a full block of possibly hundreds or thousands of bytes can be moved.
Detailed explanation-3: -Explanation: The controller raises an interrupt signal to notify the processor that the transfer was complete.
Detailed explanation-4: -The processor initiates the DMA controller by sending the memory addresses, number of blocks of data to be transferred and direction of data transfer.
Detailed explanation-5: -DMA Controllers The DMA controller then asserts a DMA request signal to the CPU, asking its permission to use the bus. The CPU completes its current bus activity, stops driving the bus, and returns a DMA acknowledge signal to the DMA controller.