DMA CONTROLLER
ARCHITECTURE OF 8085
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Question
[CLICK ON ANY CHOICE TO KNOW THE RIGHT ANSWER]
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CPU has relinquished the buses
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CPU keeps the buses
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None of Above
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CPU becomes idle
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Detailed explanation-1: -When BG = 1, the CPU has relinquish the buses and the DMA can communicate directly with the memory by specifying an address in the address bus and activating RD (read) or RW (Write) control.
Detailed explanation-2: -Bus Grant : It is activated by the CPU to Inform the external DMA controller that the buses are in high impedance state and the requesting DMA can take control of the buses. Once the DMA has taken the control of the buses it transfers the data.
Detailed explanation-3: -Removing the CPU from the path and letting the peripheral device manage the memory buses directly would improve the speed of transfer. This transfer technique is called Direct Memory Access (DMA). During the DMA transfer, the CPU is idle and has no control of the memory buses.
Detailed explanation-4: -In the cycle stealing mode, the DMA controller obtains access to the system bus the same way as in burst mode, using BR (Bus Request) and BG (Bus Grant) signals, which are the two signals controlling the interface between the CPU and the DMA controller.
Detailed explanation-5: -Address bus-carries memory addresses from the processor to other components such as primary storage and input/output devices. Data bus-carries the data between the processor and other components. Control bus-carries control signals from the processor to other components.