INTERRUPT PROGRAMMING
ARCHITECTURE OF 8085
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Question
[CLICK ON ANY CHOICE TO KNOW THE RIGHT ANSWER]
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Interrupt pin, which cannot be disabled
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INTR
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NMI
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HOLD
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HLDA
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Explanation:
Detailed explanation-1: -10.8 Non-maskable interrupt The normal interrupt mechanism of a microprocessor may be enabled and disabled by the programmer; it is said to be maskable. Usually a microprocessor has an interrupt mechanism that is not maskable, that is, it cannot be disabled by the programmer.
Detailed explanation-2: -An NMI is an interrupt which can’t be disabled by clearing the CPU’s interrupt enable flag, unlike most normal interrupts.
Detailed explanation-3: -The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable interrupt and INTR is a maskable interrupt having lower priority. One more interrupt pin associated is INTA called interrupt acknowledge.
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