INTERRUPT PROGRAMMING
ARCHITECTURE OF 8085
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Question
[CLICK ON ANY CHOICE TO KNOW THE RIGHT ANSWER]
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What are level Triggering interrupts?
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INTR &TRAP
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RST 6.5 & RST 5.5
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RST 7.5 & RST 6.5
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None of the above
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Explanation:
Detailed explanation-1: -Clock signal RST 6.5, RST 5.5, and INTR interrupt trigger in the level edge.
Detailed explanation-2: -RST 6.5 is the TRAP interrupt in the context 8085 microprocessor, it describes as none maskable interrupt. Interrupt is a mechanism by which input/output or an instruction can temporarily suspended the normal execution of processor and jump to a subrountine program.
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