INTERRUPT PROGRAMMING
ARCHITECTURE OF 8085
|
Question
[CLICK ON ANY CHOICE TO KNOW THE RIGHT ANSWER]
|
Which interrupt is not level sensitive in 8085?
|
|
RST 6.5 is a raising edge-triggering interrupt.
|
|
|
RST 7.5 is a raising edge-triggering interrupt.
|
|
|
Both A and B
|
|
|
None of the above
|
Explanation:
Detailed explanation-1: -RST7. 5 pin is an input which is edge-sensitive. Peripherals uses it for sending a pulse, rather than a sustained high level, for the interruption of the processor. Internal to 8085 we have a flip-flop which gets connected to the interrupt pin RST7.
Detailed explanation-2: -RST 7.5 is an edge triggered interrupt. It is triggered during the leading (positive) edge. The interrupts which are triggered at high or low level are called level triggered interrupts. TRAP is edge and level triggered interrupt.
There is 1 question to complete.