INTRODUCTION TO MICROPEOCESSOR
MODEL OF MICROPROCESSOR
|
Question
[CLICK ON ANY CHOICE TO KNOW THE RIGHT ANSWER]
|
All the interrupts at level 1 are polled in the second clock cycle of the
|
|
fourth T state
|
|
|
fifth T state
|
|
|
third T state
|
|
|
none of the above
|
Explanation:
Detailed explanation-1: -Explanation: All the interrupts at level 1 are polled or sensed in the second clock cycle of the fifth T state or 9th clock cycle out of 12 clock cycles. Then all the interrupts at level 0 are also polled in the same cycle.
Detailed explanation-2: -8051 has 5 interrupt signals, i.e. INT0, TFO, INT1, TF1, RI/TI. Each interrupt can be enabled or disabled by setting bits of the IE register and the whole interrupt system can be disabled by clearing the EA bit of the same register.
Detailed explanation-3: -8051 architecture handles 5 interrupt sources, out of which two are internal (Timer interrupts), two are external and one is a serial interrupt.
There is 1 question to complete.