IO AND MEMORY INTERFACE
ARCHITECTURE OF 8085
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Question
[CLICK ON ANY CHOICE TO KNOW THE RIGHT ANSWER]
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To obtain 16 bit data bus width the two 4K*8 chips of RAM and ROM are arranged in
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parallel
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serial
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both serial and parallel
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neither serial nor parallel
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Explanation:
Detailed explanation-1: -The address bus determines the number of memory locations, however the data bus determines the size of each location. So to work out the amount of addressable memory, we must multiply the number of addresses by their size.
Detailed explanation-2: -In general, linear decoding is used to minimise the required hardware.
There is 1 question to complete.