MICROPROCESSOR 8086
ARCHITECTURE OF 8085
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Question
[CLICK ON ANY CHOICE TO KNOW THE RIGHT ANSWER]
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INT0
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RST7.5
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RST6.5
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TRAP
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Detailed explanation-1: -INT0 interrupt is caused when pin no 12 in the hardware of the 8051 controller is enabled with a low levelled pulse.
Detailed explanation-2: -13 in Port 3 are for the external hardware interrupts INT0 and INT1, respectively. Memory locations are 0003H and 0013H respectively in the interrupt vector table.
Detailed explanation-3: -Which of the following combination is the best to enable the external hardware interrupt 0 of the IE register (assuming initially all bits of the IE register are zero)? For executing the EX0 interrupt, the EX0 and EA bits of the IE register should be set.
Detailed explanation-4: -8051 microcontrollers consists of two external hardware interrupts: INT0 and INT1 as discussed earlier. These are enabled at pin 3.2 and pin 3.3. These can be edge triggered or level triggered.