INTRODUCTION TO MICROPEOCESSOR
MODEL OF MICROPROCESSOR
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Question
[CLICK ON ANY CHOICE TO KNOW THE RIGHT ANSWER]
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one processor
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two processors
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more than two processors
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none of the mentioned
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Detailed explanation-1: -Explanation: In a shared bus architecture, only one processor performs bus cycle to fetch instructions or data from the memory. Explanation: The processors P1 and P2 address a multiport memory, which can be accessed at a time by both the processors.
Detailed explanation-2: -Explanation: The bus arbiter or 8289 takes care of bus access control functions and bus handshake activities.
Detailed explanation-3: -Clarification: In the prefetch stage of pipeline, the CPU fetches the instructions from the instruction cache, which stores the instructions to be executed. In this stage, CPU also aligns the codes appropriately.
Detailed explanation-4: -A bus interconnection network is a collection of processing elements (processors ) and communication elements (buses). The processors produce and/or consume messages and the buses provide communication channels to exchange messages among the processors.